| AES - |
Advanced Encryption Standard |
| AMBA – |
Advanced Microcontroller Bus Architecture |
| AHB - |
Advanced High-performance Bus |
| AMP - |
Asymmetric Multi-Processing |
| API - |
Application Programming Interface |
| ASIC - |
Application-Specific Integrated Circuit |
| ASIP - |
Application-Specific Instruction set Processor |
| AT - |
Approximately Timed |
| AV - |
Algorithmic View or Application View |
| AVM - |
Advanced Verification Methodology |
| AXI – |
Advanced eXtensible Interface |
| BCA - |
Bus Cycle Accurate |
| BFM - |
Bus Functional Model |
| CAD - |
Computer Aided Design |
| CDT - |
C/C++ Development Toolkit |
| DASC - |
Design Automation Standards Committee |
| DCT - |
Discrete Cosine Transform |
| DDF |
Dynamic DataFlow |
| DLL - |
Dynamic Linked Library |
| DMA- |
Direct Memory Access |
| DMI - |
Direct Memory Interface |
| DPI - |
Direct Programming Interface |
| DSL - |
Digital Subscriber Line |
| DSP - |
Digital Signal Processor |
| DTD - |
Document Type Definition |
| ECIX - |
Electronic Component Information eXchange |
| EDA - |
Electronic Design Automation |
| EDK - |
Embedded Development Kit |
| EHCI - |
Enhanced Host Controller Interface |
| ESL – |
Electronic System Level |
| eRM - |
e Reuse Methodology |
| FDM - |
Frequency Division Multiplexing |
| FIFO – |
First In First Out |
| FIR - |
Finite Impulse Response |
| FLIX - |
FLexible
Instruction eXtensions |
| FPGA - |
Field Programmable Gate Array |
| FPU - |
Floating POint Unit |
| FSM - |
Finite State Machine |
| GP - |
Generic Payload |
| GUI - |
Graphical User Interface |
| HAL - |
Hardware Abstraction Layer |
| HDL – |
Hardware Description Language |
| HVL - |
Hardware Verification Language |
| HW/SW - |
HardWare/SoftWare |
| ICE - |
In-Circuit Emulator |
| IDCT - |
Inverse Discrete Cosine Transform |
| IDE - |
Integrated Development Environment |
| IJG - |
Independent JPEG Group |
| IP – |
Intellectual Property |
| IPCM - |
Incisive®
Plan-to-Closure Methodology |
| ISA - |
Instruction Set
Architecture |
| ISR - |
Interrupt Service Routine |
| ISS – |
Instruction Set Simulator |
| ITF - |
Interpret-Translate-Feedback |
| JIT - |
Just In Time |
| JPEG - |
Joint Photographic Experts Group |
| KPN - |
Kahn Process Network |
| LAU - |
Least Addressable Unit |
| LT - |
Loosely Timed |
| LTE - |
Long Term Evolution |
| MAC - |
Multiply ACcumulate |
| MIMO - |
Multiple-Input Multiple-Output |
| MOC - |
Model Of Computation.
Sometimes written MoC |
| NOC - |
Network On Chip.
Sometimes written NoC. |
| NRE - |
Non-recurring
Engineering |
| OCP - |
Open Core Protocol |
| OCP-IP - |
Open Core Protocol International Partnership |
| OFDM - |
Orthogonal Frequency Division Multiplexing |
| OS - |
Operating System |
| OSCI - |
Open SystemC Initiative |
| OPB - |
On-chip Peripheral Bus or Open
Peripheral Bus |
| OTG - |
On-The-Go |
| OVM - |
Open Verification Methodology |
| PBD - |
Platform Based Design |
| PLB - |
Processor Local Bus |
| PLD - |
Programmable Logic Device |
| PLI - |
Program Language Interface |
| PSL - |
Property Specification Language |
| PV - |
Programmer’s View |
| PV+T or PVT- |
Programmer’s View plus Timing |
| RAM - |
Random Access Memory |
| RASSP - |
Rapid-prototyping of Application Specific Signal Processors |
| RDL - |
Register Description Language |
| RMS - |
Root Mean Square |
| ROI - |
Return-On-Investment.
Sometimes called RoI |
| RTL - |
Register Transfer
Level |
| RTOS - |
Real Time
Operating System |
| SAHE - |
Software Accessible Hardware Elements |
| SCE-MI - |
Standard Co-Emulation – Modeling Interface |
| SCV - |
SystemC Verification library |
| SDK - |
Software
Development Kit |
| SDL - |
Specification and Description Language |
| SEC - |
Sequential Equivalence Checking |
| SIMD - |
Single Instruction Multiple Data |
| SLVP - |
System-Level Virtual Prototype |
|
synonymous with
functional prototype or virtual system prototype |
| SMP - |
Symmetric Multi-Processing |
| SNR - |
Signal-to-Noise Ratio |
| SoC – |
System on Chip.
Sometimes called SOC. |
| SPIRIT - |
Structure for Packaging, Integrating and Re-using IP with
Tools-flows consortium |
| SQNR - |
Signal-to-Quantization Noise Ratio |
| STL - |
Standard Template Library |
| SVA - |
SystemVerilog Assertions |
| TIE - |
Tensilica Instruction Extension |
| TL - |
Transaction Level |
| TLI - |
Transaction Level Interface |
| TLM - |
Transaction Level Modeling |
| TLP - |
Transaction Level Platform |
| TME – |
Technical Marketing Engineer |
| URM - |
Universal Reuse Methodology |
| USB – |
Universal Serial Bus |
| UML - |
Universal
Modelling Language |
| VCT DWG - |
Virtual Component Transfer Development Working Group |
| VCX - |
Virtual Component eXchange |
| VHDL - |
VHSIC hardware description language |
| VHPI - |
VHDL Procedural Interface |
| VIP - |
Verification IP |
| VLIW - |
Very Long Instruction Word processor |
| VRE - |
Virtual platform Runtime Environment |
| VSIA - |
Virtual Socket Interface Alliance |
| VMM - |
Verification Methodology Manual |
| VSP - |
Virtual System Prototype |
|
synonymous with
functional prototype or system-level virtual prototype |
| VV - |
Verification View |
| XCL - |
Xilinx
Cache Link |
| XML - |
eXtensible Markup Language |
| XPG - |
Xtensa Processor Generator |
|
|