Chapter 9 C/C++ hardware design for the real-world

In previous chapters we have seen how system level virtual prototypes get created and how they are often partitioned into pieces intended to be implemented as either software or as hardware. This partitioning was done to manage costs, performance and to optimize many other attributes of the system. For the parts of the system intended to be hardware, several choices still remain. It is possible that those functionalities can be implemented using off the shelf components, such as processors or DSPs, or as components that require small extensions in order to meet the necessary requirements, such as configurable and extensible processors. It is likely that there will be a few components for which dedicated custom hardware is required and we now need to refine those models in ways that make them more amenable to the transformation process that is often called behavioral synthesis, or high-level synthesis. [BIB COUS 08]

This chapter will talk about both the manual transformations of the models that are necessary and also demonstrate the power of the commercial tools that are available. To get the most from those tools, the user must understand what this transformation process is about and guide the tool towards the right implementation. High-level synthesis involves the manipulation of many interrelated aspects of the hardware generation process and the technology is not yet at a level where it can automatically find an optimized solution without expert guidance. This chapter aims to provide you with the knowledge that you need to be able to generate a good solution.

In order to demonstrate the process, we will be showing the Catapult® C Synthesis tool from Mentor Graphics. [BIB BOLLAERT]. As with the other demonstration chapters of this book, Catapult is not the only high-level synthesis tool on the market, but it is necessary to concentrate on one tool in order to explain more than just general concepts. If after reading this chapter you believe that high-level synthesis can provide you with the productivity gains that you are looking for, then you should perform a complete analysis of all of the tools available to you.

Mentor Graphics has a long history in the development of high-level synthesis. Their attempts to break into the RTL synthesis market with Autologic in the early 1990s were never successful, even though they tried several times. Synopsys' Design Compiler had a tight grip on the market and even significant improvements in algorithms or performance were not enough to shake the Synopsys dominance in the marketplace. Mentor has a business philosophy that it wants to be number one or two in a market and if it cannot achieve that, then it considers the market to be too difficult to navigate. Because of this, Mentor often looks for markets that are underserved by the other companies, and this led them to examine the FPGA synthesis market. Their equity purchase of Exemplar back in 1995 and complete purchase in 1999 gave them a solid foundation on which to build other synthesis technologies. Mentor made their first attempt in the high-level synthesis market in 1997 with Monet. This was based on VHDL as its input language, a language that was used by many Mentor customers, and thus seemed to be a logical choice. They did attract a number of users, but not enough to warrant making it a permanent member of the Mentor tool line-up. Even though this product was not successful, Mentor went back to the drawing board with it, and the technology resurfaced as Catapult C synthesis in 2004. This revised product had been the result of quietly working with customers through the intervening period, and when the product was announced they already had a significant number of endorsements lined up for the launch, and could claim 10 product tape-outs that had successfully deployed it. Now if you do a search for Catapult on the Internet, you will find piles of customer endorsements, certifications for ASIC libraries or integrations with other related tools. For a more complete history of the progress of high-level synthesis in general, and other solutions that are available in the marketplace, the reader should refer to ESL Design and Verification [BIB BAIL 07] - chapters 3 and 11 and [BIB BOLLAERT].

9.1 Introduction
     9.1.1 Chapter overview
9.2 Where does it fit in an ESL flow
     9.2.1 Hardware implementation input
     9.2.2 High-level synthesis output
     9.2.3 Verification models
     9.2.4 Other uses for the input model
9.3 Why C/C++/SystemC
     9.3.1 Language limitations for Synthesis
9.4 High-Level Synthesis Fundamentals
     9.4.1 Schedule and allocation tradeoffs
     9.4.2 Synthesis at the interface
     9.4.3 Hierarchy
     9.4.4 Other control
     9.4.5 Target library
     9.4.6 Data type Libraries for Synthesis
     9.4.7 Synthesis Tools
9.5 Synthesis domains
9.6 A simple example
     9.6.1 Embedded Architecture
9.7 Tying it in to a verification flow
     9.7.1 Verification with simulation
     9.7.2 Verification with equivalence checking
     9.7.3 Verification against algorithmic model
     9.7.4 Verifying power
9.8 A more complex example
     9.8.1 The Application
     9.8.2 The Flow
     9.8.3 Design
     9.8.4 Verification
     9.8.5 Synthesis
     9.8.6 Results
     9.8.7 Results analysis
9.9 Successful adoption
9.10 The future
9.11 Summary
9.12 References

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