Chapter 6 Processor-centric design: Processors, Multi-processors and software

Almost all embedded systems are a combination of software running on embedded processor cores, supporting hardware such as memories and processor buses, and other hardware elements including function accelerators and peripheral interface blocks. As a result, systems design increasingly is taking a processor-centric focus. High-level descriptions of systems functionality must be analyzed and partitioned across multiple elements, including processors, potentially more than one, and hardware components where needed.

After the system is partitioned, various components are implemented and integrated. Implementation may be based on reusable, configurable hardware and software IP, or may required development from scratch. The system may not be fully specified at initial design time, because it may be intended to be a reusable product platform. In this case, in order to accommodate additional functionality unspecified at design time, extra processing resources need to be designed in.

There are many options for designing instruction set processors for such systems, including use of fixed [ACR] instruction set architecture (ISA) processors, use of multiple processors either homogeneous or heterogeneous, or the design of [ACR] application specific instruction set processors (ASIPs) either from scratch, or based on configurable and extensible processor IP. Ensuring a successful product design and implementation after choosing one or more of these options can be a complex juggling act of many different issues.

This chapter looks into the issues involved in processor centric design using a commercial configurable and extensible processor IP as an example. It will start with a particular, quasi-realistic design application and illustrate the steps taken in a design and implementation flow using a particular set of ESL design tools for processor-centric systems, showing how various options are chosen and issues are resolved.

6.1 Choices and tradeoffs in processor-centric design
6.2 An ASIP Integrated Development Environment (IDE)
6.3 Introduction to flow and example
6.4 Starting with algorithms
6.5 Processor definition
     6.5.1 Designing the design space exploration
     6.5.2 Exploring the processor design space: pre-configured cores
     6.5.3 Exploring the processor design space: automatically
     6.5.4 Exploring the processor design space: cache and memory
     6.5.5 Exploring the processor design space: fine-tuning
     6.5.6 Speed-area-power tradeoffs
     6.5.7 Detailed Energy Space Exploration
6.6 Software implementation
6.7 Predicting software performance via sampling
6.8 Multicore issues
     6.8.1 A practical methodology for multiprocessor ASIP definition and programming
     6.8.2 Developing multicore system level models
     6.8.3 Porting methodology for new video codecs to the multicore system
     6.8.4 Using the IDE for multicore simulation and validation
6.9 Debug
     6.9.1 Single core debug in the IDE
     6.9.2 Multi processor debug in the IDE
6.10 Conclusions
6.11 References

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