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This chapter deals with producing a hardware implementation of
a component of a design. In other chapters, we have seen the process
of designing and analyzing a system at the ES level, and partitioning
the system functionality into hardware and software. The purpose
of this partitioning is to improve the overall performance, power,
and area characteristics of the system in addition to making the
size of the partitioned pieces suitable for implementation. There
are a number of different implementation technologies that can
be used for any part of the system functionality:
，PU: The function can be executed as software on a
general-purpose CPU such as an ARM, MIPS or Tensilica Diamond
core.
・PU (Extensible Processing Unit): The function can be executed
as software on an extensible processor in which specialized instructions
have been added for the particular algorithm.
．SP: The function can be executed as software on a specialized
DSP such as a Texas Instruments TMS320 or StarCore SC2400.
〃LIW processor: The function can be executed as microcode on
a specialized VLIW processor.
：PGA: The function can be implemented in configurable hardware
such as an FPGA core.
、SIC: The function can be implemented as dedicated hardware in
custom gates.
Each of these options has different power, performance, and programmability
characteristics. Partitioning the SoC functionality among these
implementation technologies consists of seeking a balance between
performance and power on the one hand and programmability on the
other, as defined in Chapter 2, and discussed
in Chapters 8 and
9. Other factors that enter into this decision include manufacturing
cost due to silicon area, and the cost of licensing any required
IP.
11.1 Introduction
11.2 Extensible Processors
11.3 DSP Coprocessors
11.4 Customized VLIW Coprocessors
11.5 Application-Specific Coprocessors
11.6 High-Level Hardware Design Flow for ASICs and FPGAs
11.7 Behavioral Synthesis
11.7.1 Differences between RTL and Behavioral
Code
11.7.1.1 Multicycle
Functionality
11.7.1.2 Loops
11.7.1.3 Memory
Access
11.7.2 Behavioral Synthesis Shortcomings:
Input Language
11.7.3 Behavioral Synthesis Shortcomings:
Timing
11.7.4 Behavioral Synthesis Shortcomings:
Verification
11.8 ESL Synthesis
11.8.1 Language
11.8.1.1 Structure
11.8.1.2 Concurrency
11.8.1.3 Data
Types
11.8.1.4 Operations
11.8.1.5 Example
11.8.2 Input and Output
11.8.3 Verification
11.8.4 Quality of Results
11.8.4.1 Timing
11.8.4.2 Scheduling
11.8.4.3 Allocation
11.8.4.4 Back-End
Friendliness
11.8.4.5 Example
Results
11.9 Hardware Design or Silver Bullet?
11.9.1 Role of Constraints
11.9.2 Pragmas
11.9.3 Code Changes
11.9.4 Example
11.9.4.1 Constraints
11.9.4.2 Code
Modification
11.10 Design Exploration
11.11 Provocative Thoughts
11.12 Summary
11.13 The Prescription
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